By Vijay Chobisa, Senior Director Product Marketing at Siemens.
Emulation and prototyping are foundational elements of a project team’s verification strategy, be it for high- performance compute, artificial intelligence (AI) accelerators, or communication chips, effectively verifying and validating that those chips will work as intended.
Both types of hardware- assisted verification (HAV) tools have been around since the 1980s. In the last decade, they have come out of the dusty back corners of IT centers and firmly refuted their questionable value. No one disputes their value any longer.
There are several reasons for this about face. Foremost, the chip design and verification landscape has changed because of design scale, demands of data center CPUs and GPUs, AI accelerator applications, and the size and complexity of software stacks.
Also, the chip is often not the product. The product is the system with a full software stack that the design group must verify. That’s because system houses are designing purpose-build SoCs and have different expectations from traditional IC design companies. Their product is the chip on its board running its entire software stack from drivers and operating systems up through applications—an integrated system that must be tested in its entirety, not just modules of the RTL code. These SoCs are designed to execute specific software workloads effectively and deliver on a power/performance matrix.
As a result, an integrated HAV platform with hardware emulation and FPGA prototyping becomes an essential component of these verification environments and continues to evolve to meet demands of this new generation of leading-edge designs.
Make no mistake. Hardware emulation and FPGA-based prototyping have distinct attributes, are implemented differently, and are not interchangeable. They arecomplementary with specific functions in a verification flow. Hardware engineers and software developers select the HAV system for a specific task since each task has unique requirements for faster time-to-project completion and lower cost per verification cycle. Logic designers use an emulator to integrate IP and for chip-level verification. Software developers attempt to boot an operating system on the chip design using the prototyping platform. Both are often used on the same projects. Hardware emulators are based on purpose-built SoCs or large FPGAs that may be commercial or custom-designed, depending on the vendor.
The chips have different attributes that give emulation platforms distinct capabilities, particularly verifying and debugging the interaction of hardware with software in SoC designs in ways that no other solution can. With an ease of compiling RTL into an executable model and its full observability of signals, they are ideal forRTL design and verification.
Prototyping tools utilize different FPGAs than emulators with varying performance metrics based on the vendor. They achieve greater execution speed than emulation in exchange for less flexibility and observability.
Prototyping, a vital tool for software developers who must validate their code against the RTL design, continues to accelerate firmware, operating system, application development, and system integration tasks. A recent innovation in FPGA prototyping is a scalable system-wide enterprise prototyping system with capacity ranging from 40-million gates to more than 40-billion gates.
Just like emulation and prototyping, one HAV system is not interchangeable with another. Nor is one like the next, either. And they continue to evolve. One new HAV architecture unifies hardware emulation, enterprise prototyping, and at-speed software prototyping to accelerate verification and validation cycles into a single system. The integration offers congruency, speed, and modularity, accelerating verification and validation cycles while reducing the cost-per-verification cycle. The system features a purpose-built accelerator chip for emulation and an FPGA adaptive SoC for enterprise and software prototyping.
RTL designers, software coders, and system-level engineers can effectively collaborate and communicate using a common user interface, models, and database. Each system meets the demands of its role in the design process with distinct attributes and different implementations.
Many HAV systems are built for congruency, shareability, capacity, scalability, and speed, giving engineers access to the right tool for the right task with benefits for both small and large designs.
Congruence is implemented across integrated HAV systems so that an RTL model will compile to produce the same behavior in each, just at different execution speeds and levels of observability. Congruency enables a seamless move between HAV platforms.
Shareability is also a standard feature in HAV systems and important for the overall enterprise rather than one engineering group using the system. As enterprise- class environments, these systems can support multiple groups or design projects around the globe.
An HAV’s scalability offers maximum capacity and granularity, since leading- edge designs—whether small or large, monolithic or multi-die—can comprise tens of billions of gates. Many small designs consume the HAV system’s capacity and require proper environmental set up. Large designs need reliable and steady access to large capacity to be able to compile the entire design, handle large workloads, and complex debug.
Performance is a feature/ benefit on today’s HAVs for execution speed and compile speed. HAV performance enables running long complex workloads not only for functionality but for power- performance analysis.
Chiplets are another emerging use case—an incredible opportunity to design a complex system mixing and matching functionality that is not just logic devices and an opportunity for HAV platforms. Chiplet verification is similar but different than verifying multiple sources on the system. A chiplet includes fabric, interconnect, and capacity. The challenge is its capacity scaling and reliability, and it is binary. Both can be managed using HAV platforms.
Designs are large and interactions between the chip and the system are complex. Verification now encompasses conventional RTL verification and validation of the entire system that includes proving correct operation of the full software stack often with application code. This requires verification of interactions between the chip, its board, and mechanical subsystems within the overall design.
Projects of this scale require hardware, software, and system-level co-design and co- verification. This is why a project team needs an emulation platform, enterprise prototyping platform, and an at-speed prototyping platform delivered as a full HAV system environment.