SWA provides a way to reduce cost, reduce space, and increase the reliability of the system.

Many of today’s electronic systems involve two or more printed circuit boards (PCBs). A perennial problem for system designers is connecting the boards together to transfer data between them. A very common solution is to mount multi-pin connectors on the boards and to use multi-wire harnesses or flex to link them together.

Unfortunately, each connector pin is a potential point of failure.Thus, in addition to adding cost and consuming space, connectors are often the overwhelming factor regarding the reliability—or lack thereof—in an electronic system. Contra wise, minimizing the number of inter-board connections reduces cost, reduces space, and increases the reliability of the system. Not surprisingly, designers of a wide range of systems—from handhelds to notepad computers to industrial controllers— desperately wish to minimize the number of connector pins and inter-board wires.

One point worth noting is that many of these inter-board signals typically provide only relatively low speed communications using general-purpose input/outputs (GPIOs) or serial interfaces like I2C (inter-integrated circuit) and I2S (integrated inter-IC sound bus).

Single wire aggregation
The idea behind single wire aggregation (SWA) is to take multiple signals and aggregate them into a time division multiplexed (TDM) signal that requires only a single inter-board wire. One way to do this would be to create a custom application- specific integrated circuit (ASIC) for each product.

Unfortunately, there are multiple disadvantages associated with custom ASIC solutions, including the fact that they are expensive and time-consuming to develop. Even worse, any algorithms and functions they contain are effectively “frozen in silicon,” which means they cannot adapt to changing requirements, such as the head of sales unexpectedly announcing: “Our biggest customer says we need to replace one of the I2S interfaces with two I2C channels.”

The solution is to use low- cost field-programmable gate arrays (FPGAs), such as iCE40 UltraPlus devices from Lattice Semiconductor. One huge advantage of using FPGAs to implement single wire aggregation is that they are extremely flexible and can be quickly and easily customized to implement the required numbers and types of the various communications channels.

The statement in the preceding paragraph—that FPGA-based SWA solutions can be quickly and easily customized—comes with
a small caveat, which is that you have to be familiar with designing FPGAs.

If you are an FPGA designer, in the case of its SWA solution, Lattice provides full reference design resources for use with its industry-leading iCE40 UltraPlus FPGAs:

• Thesourcecodefor an easily modifiable parameterized SWA reference design ready to run on the Lattice Radiant design tool.

• Free access to the Lattice Radiant design tool.

• An associated Reference Design User Guide.

• An SWA demonstration and development board.

Unfortunately, not every design team has access to FPGA design expertise. Fortunately, Lattice also has solutions for non- FPGA designers.

SWA for non-FPGA designers
FPGA designs are captured using hardware description languages (HDLs) like Verilog or VHDL, and then running a hardware compiler called a logic synthesis engine, which takes the HDL and generates a configuration file, also known as a bitstream. Anyone can load this bitstream into the FPGA without having to know anything about designing FPGAs.

The first SWA solution for non- FPGA designers is based on Lattice providing a suite of five pre-synthesized bitstreams. These configurations, which are based on an analysis of multiple real-world products, have been selected to address the requirements of a wide range of system designs.

A Bitstream User Guide is available from Lattice’s SWA webpage (https://bit. ly/3O5Blaw).This guide describes how anyone can load one of the preconfigured bitstreams into an iCE40 UltraPlus FPGA. But wait, there’s more, because Lattice also offers a free SWA design service. If you visit Lattice’s SWA development board webpage (https://bit. ly/37KsISc), you can use an interactive form to specify the unique combination of channels you require for your design, and the Lattice design team will email the corresponding bitstream file to you.

iCE40 UltraPlus FPGAs
In addition to featuring an ultra-low-power advanced process with static current as low as 75μA and as little as 1 to 10mA active current for most applications, iCE40 UltraPlus FPGAs are also available in multiple package options to fit wide range of applications needs, from an ultra-small 2.15 x 2.50mm WLCSP package optimized for consumer and IoT devices to a 0.5 mm pitch 7 x 7mm QFN for cost-optimized applications.

Of particular interest is the fact that the configuration bitstream can be loaded directly into SRAM-based configuration cells, thereby allowing iCE40 UltraPlus FPGAs to be reprogrammed over and over again.This is the best option during the prototyping phase of a project because it allows you to experiment with different designs and bitstreams.

If the SRAM-based configuration approach is used when the iCE40 UltraPlus is deployed in a product, then the configuration can be loaded via an on-board MCU or from an external SPI Flash memory device. Alternatively, iCE40 UltraPlus FPGAs also contain a one-time programmable (OTP) on-chip non-volatile configuration memory (NVCM), which is best suited for mass production. Once the NVCM has been programmed, the device will automatically, quickly, and securely boot from this configuration.

Bits and Bytes
The single wire communication between the FPGAs runs around 7.5 megabits-per-second (Mbps).The design is also configurable—the number of I2C/I2S busses and GPIOs and single wire protocol packet length can be adjusted, and
the single wire protocol between the FPGAs is robust with error detection and retry features. A brief summary of the various features is as follows:

• Up to seven channels can be aggregated.

• The raw data rate on the single wire interface is ~7.5Mbps or higher.

• The system supports variable packet length for efficient use of the single wire bandwidth.

• A retransmit feature is offered when a parity error is detected on the receiver side.

• The system supports both I2C Fast-mode (400kbps) and Fast- mode Plus (1Mbps).

• I2C Interrupts can be realized using GPIO with event-based transmission.

Summary
Many of today’s electronic systems involve multiple circuit boards. Furthermore, many of these systems use multiple interfaces of different types—like I2C, I2S, and GPIO—to collect data from peripherals and sensors and to communicate this data between boards.

Lattice has developed an innovative new way for system architects and developers to use tiny, low- cost FPGAs to implement single wire aggregation, which can dramatically reduce the number of inter-board connections, thereby increasing the reliability of the system while also reducing its size and cost.This solution can be customized by developers with FPGA design experience. Even better, it can be quickly and easily deployed by developers with no FPGA experience whatsoever!

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