GOWIN takes a new direction with its low-density FPGAs.
By Danny Fisher, Director of International Marketing at GOWIN Semiconductor.
High-end FPGAs are at home in the world of multi- gigabit-per-second signal conversion and bridging. In high-bandwidth telecoms, network, and data center equipment, the FPGA is a mainstay of system designs. These very fast and large chips provide hundreds of inputs and outputs (I/Os), huge bandwidth, and built-in standard interfaces. The fact that they are also expensive and power-hungry is a bearable trade-off for telecoms and network equipment manufacturers.
Increasingly, however, the need for multi-gigabit- per-second rates in signal bridging systems is extending from telecoms and network equipment into consumer and industrial devices. Here, too, the FPGA offers valuable benefits. But large, expensive, power- hungry components are a poor fit for sleek, battery- powered consumer devices in the ultra-competitive markets for products such as tablets, laptop computers, and augmented/virtual reality (AR/VR) headsets.
This new demand in consumer electronics is forcing FPGA manufacturers to rethink the architecture of their products in a bid to provide high-speed SerDes functionality at lower cost and low power.
Gamers lead the way The change that has precipitated a new wave of competition in the low-cost FPGA market has been led by demand from gamers: tablets and laptop computers have become the latest devices in which users want to play games in 4K resolution and—for smooth rendition of fast motion—at high frame rates of up to 160 frames/s.
Many tablets use a system-on-chip (SoC) device originally made for smartphones. This SoC’s display output signal needs to be converted to support a tablet’s larger 4K display— an ideal role for a low-end FPGA. Other use cases are also starting to demand increased bandwidth in the link between an SoC and one or more displays, or between image sensors and an SoC. Examples include:
• Point-of-sale systems: Splitting a single output from an SoC (typically in MIPI DSI format) to drive dual displays, one facing the consumer, the other facing the sales counter. An FPGA typically converts the single DSI input to one DSI and one eDP output, with image processing to rescale the output and adjust the frame rate.
• VR/AR headsets and goggles: Splitting and converting a DisplayPort- over-USB Type-C input from a host device such as a PC or smartphone to separate MIPI outputs to a left and right display in the headset.
• Industrial machine vision systems: Converting an image sensor’s MIPI D-PHY or C-PHY input to a high-speed USB 3.0 output to a host computer.
Higher-speed SerDes at lower power and cost In all these use cases, an FPGA can provide the raw SerDes throughput for one or multiple display screens or image sensors, all while enabling changes in the input or output specifications to be made just by changing the VHDL or Verilog programming of the device. The question the consumer and industrial markets are asking is, how far can power consumption, size, and cost be reduced while still providing the high SerDes bandwidth these applications require?
GOWIN has provided a new answer to this question by combining application- specific optimizations at both the silicon and circuit design levels in ways that no low-density FPGA has previously attempted.
In silicon, scaling provides PPAC benefits (power, performance, area, and cost) for low-end FPGAs as much as for other semiconductors. In the past, however, low-density FPGAs have tended not to take advantage of more advanced process nodes— FGPA manufacturers have preferred to extend the life of IP developed for legacy processes.
But high-speed video bridging places extreme demands on the FPGA. That is why for its Arora V products, GOWIN shifted production from the 55nm process used in its Arora II products to TSMC’s ultra- low power 22nm process.
Use of this process has enabled GOWIN to gain performance, power and cost benefits in low-density Arora V products, such as the GW5AT-15, which is available in a compact 4.9mm x 5.3mm WLCSP package. Despite its small size, this FPGA integrates various hard-core SerDes transceivers offering maximum SerDes throughput of 12.5Gbps, together with 15,120 logic elements (Les) alongside high-speed memory resources including:
• 118kb of shadow SRAM. • 630kb of block SRAM (BSRAM) arranged as 35 x 18kb.
• Optional 64Mb (in MG132P package) or 128Mb (in CM90P package) of pseudo SRAM (pSRAM).
By limiting the programmable logic provision to 15,120 LEs, GOWIN can produce a smaller die at a lower unit cost, while still providing sufficient digital capability to perform important image processing functions such as frame scaling and frame rate adaptation.
The application-specific circuit design optimizations in the Arora V family provide the higher SerDes throughput required by gamers viewing 4K content at 160 frames/s on a tablet, for example. In many new 4K gaming tablet designs, MIPI C-PHY is replacing the earlier D-PHY interface because of its higher bandwidth. To meet this requirement, the GW5AT-15 includes a hardcore three-lane MIPI C-PHY interface that transfers data at 5.7Gbps/lane.
Other hardcore interfaces in this FPGA are:
• Four-lane MIPI D-PHY (2.5Gbps/lane).
• x4 PCIe 2.0.
Alongside these circuit features, the GW5AT-15 includes various built-in softcore interfaces suitable for video bridging applications: a USB 2.0 PHY, a USB 3.0 PHY, PCIe 3.0, and up to four lanes of 12.5Gbps/lane SerDes suitable for DisplayPort, eDP, SLVS-EC, LVDS, and other types of video traffic.
In a gaming tablet rendering 4K video at a high frame rate, for example, the GW5AT-15 may be used to convert a typical SoC’s MIPI output to the tablet display’s eDP input.
A new direction for low-density FPGAs The optimization of an FPGA product for video bridging and image processing applications points this segment of the low-density FPGA market in a new direction. In pursuit of greater reduction in terms of size, power, and cost, FPGA products are evolving to include more application-specific SerDes functionality hard-wired into small devices.
Previously, FPGAs achieved low cost by maintaining older, legacy silicon fabrication processes. Now, a new generation of low-density FPGAs are using advanced processes to provide the valuable advantages of low power and small footprint while reducing cost by limiting the provision of logic elements that are not required in the target applications.
This brings the FPGA to center stage in the consumer device market, enabling a new generation of devices to benefit from improved display and camera performance without sacrificing battery power or competitive cost.