A compact, easy- to-implement FPGA development option.
By Adam Taylor, founder and Principal at Adiuvo Engineering and Training.
Designing FPGA-based systems involves navigating several technical challenges, including managing multiple power supplies, power sequencing, clocking,configuration memories, and I/O allocation. These factors can be daunting, especially for developers unfamiliar with hardware integration.
One common approach to mitigate these risks involves development boards, which allow engineers to begin hardware testing early in the design process. For the larger and more complex FPGAs, such as Zynq UltraScale+ or Versal, System-on-Modules (SoMs) are sometimes used to simplify hardware development. Until now, however, there has not been a similar, ready-to-use option for smaller FPGA devices.
We recently developed our Spartan 7 FPGA Tile aiming to address this gap by offering a pre-engineered module designed for integrating Spartan 7 devices into systems while reducing associated technical risks.
Features and design
The Spartan 7 FPGA Tile features an AMD Spartan 7 FPGA along with essential components like power supplies, clocking, configuration and user memories, and I/O breakout (including single-ended and differential signals). We designed the module to be as compact as possible (it measures only 59mm x 59mm). This tile offers developers the ability to hit the ground running, with reduced technical risk.
The tile can be programmed via USB JTAG or direct JTAG. Power-wise, the tile operates from a single 5V nominal power supply. Comprehensive documentation—including user guides, schematics, and reference designs—supports developers in getting started quickly, without needing to dive deeply into the FPGA’s underlying hardware architecture.
Performance and capabilities
At its core, the FPGA features 23K logic elements, 80 DSP slices, and 45 BRAM blocks, making it suitable for a range of tasks from basic control algorithms to more intensive applications like signal filtering and I/O expansion. Despite its compact size, the tile provides the processing capabilities demanded by many embedded applications.
Application areas
The tile’s design allows it to serve in a variety of roles, such as a system controller handling power supply sequencing and power monitoring, as well as managing configuration processes for more complex FPGAs or processors such as Versal or Zynq MPSoC devices. In this role, the tile can monitor sensors, control peripherals, and ensure the more expensive and valuable components are protected and operated safely.
Other potential use cases include sensor aggregation, where data from multiple sensors can be collected and processed, and I/O expansion. Additionally, it has potential applications in offloading intensive processing tasks such as signal processing or encryption, and it can be used for protocol conversion in systems where legacy and modern protocols need to coexist.
RISC-V microcontroller IP
One notable feature of the Spartan 7 FPGA Tile is its ability to implement a soft RISC-V microcontroller. This adds flexibility, particularly for developers who need both FPGA and microcontroller functionalities in their designs. The RISC-V IP core uses less than 15% of the available logic resources,leaving sufficient capacity available to implement many other functions.
When using this RISC-V based approach, we are also able to deploy machine learning in the form of TinyML on the tile, further supporting system controller applications using prognostic and predictive maintenance.
Conclusion
Using this tile enables developers to reduce their technical risk and development timescales. Furthermore, we have similar tiles in development that will offer a variety of FPGAs in the same footprint (watch this space).