Today’s SoCs are so complex they need a network-on-chip (NoC)

By Clive “Max” Maxfield, Editor at DENA, CTO of LogiSwitch, and freelance technical writer and consultant.

In the same way that “there’s no point reinventing the wheel,” there’s no reason for the developers of system-on-chip (SoC) devices to redesign well known functional blocks like application processors (APs), encryption engines, video codecs, and communications functions (Ethernet, I2C, SPI, USB). Instead, the developers prefer to acquire these functions from third-party vendors, leaving them free to focus on designing their own “secret sauce” IP that will differentiate their device from their competitors’ offerings.

IP blocks must be connected in some way so they can talk to each other. When SoC developers first started to use third-party IP, a typical design might contain only a few handfuls of such blocks. A common approach circa the 1990s was to use a bus-based architecture. This remains a useful technique for today’s simpler designs involving only one (or very few) initiator blocks talking to a limited number of target blocks, where all the blocks employ the same interface (i.e., the same bus widths running at the same frequency with the same protocol).

As designs started to include more and more initiator and target blocks, bus-based architectures began to run out of steam. Circa the 2000s, many design teams transitioned to using crossbar switch-based interconnect architectures. In this case, any initiator block can talk to any target block and multiple transactions can be in flight at the same time. Furthermore, in the case where multiple transactions arrive at the same switch, that switch has the ability to prioritize transactions, buffering those with a lower priority while handling those with higher priority.

Not so long ago, an entire SoC might boast only 20,000 to 50,000 logic gates and registers. Today, by comparison, a high-end SoC can contain hundreds of IP blocks, each of which may comprise hundreds of thousands (sometimes millions) of logic gates and registers. In fact, I was recently introduced to an SoC design containing more than a billion gates!

When it comes to this class of design, even crossbar switches are starting to bite the dust due to the amount of silicon real estate they consume and the routing congestion resulting from their underlying architecture. An even bigger problem is that the various IP blocks may support different interfaces (widths, frequencies, protocols).

One solution that is increasingly being adopted by today’s high-end design teams is to employ a network-on-chip (NoC). In this case, the IP blocks communicate by passing packets back and forth, where each packet contains its destination and its payload data. Each IP block interfaces with the NoC by means of a “socket,” which handles things like width conversion, protocol conversion, command translation, and clock domain crossing (different IPs can be running at different frequencies).

Unfortunately, creating a NoC from the ground up is a non-trivial task. In fact, it could take as long to develop the NoC as it does to design the rest of the device. Happily, off-the-shelf solutions are at hand in the form of third-party NoC IP, such as FlexNoC from Arteris IP.

All I can say is that things have come a long, long way since I was a young designer.

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