Designers are faced with conflicting demands for higher functionality while consuming less power.

Smart devices are spreading everywhere and, whether they run from mains electricity, a battery, or energy harvesting, minimising their power and energy requirements is critical, both to ease the management of large numbers of devices and to “green” the IoT edge.

On the other hand, each successive generation—whether a smart sensor, IoT gateway, autonomous controller, smart appliance—is expected to provide more capabilities and capacity, handle more complex situations more intelligently, and respond more quickly. Traditionally, microcontrollers have been the main choice in power-conscious systems such as those used in IoT applications. However, with the increasing demand of processing power, microprocessors are being sought out.

Using the latest embedded processors to minimise power consumption

As the apparently conflicting demands for lower power with greater performance and sophistication intensify, frugal power management is increasingly important using techniques like granular low-power operating modes with the gating of clock signals to halt specific peripherals and the power gating of unneeded domains to avoid leakage current.

Chip designers refine and improve these techniques with each generation of devices. In addition, further innovations continue to extend the power-conscious embedded designer’s toolbox; like the Energy Flex architecture of the i.MX 8ULP and i.MX 8ULP-CS families announced recently by NXP.

As well as the intrinsic energy savings gained through the latest 28nm FD-SOI process technology, the Energy Flex architecture features advanced design techniques and heterogeneous domain processing. Application-level processing running a rich operating system (OS) on the chip’s Cortex-A35 cores is separated from real-time processing managed by a real-time OS (RTOS) running on the Cortex-M33 embedded-class core. An optional Fusion DSP in the real-time domain handles low-power keyword detect, and there is a separate Flex domain with a HiFI 4 DSP for advanced audio and voice processing. Altogether, Energy Flex improves efficiency by up to 75%.

Then there is the µPower subsystem, controlled by a dedicated core, which is implemented specifically to handle power management. This can manage more than 20 different power-mode configurations across processing domains, thereby helping developers properly utilize the flexible power-saving opportunities available.

Power-management features in i.MX 8 Processors

The features of the new ultra-low-power (ULP) devices build on techniques employed in other i.MX processors—such as the i.MX 8 families—to minimize wasted power. The Arm platform, L2 cache, phase-locked loop (PLL), and peripherals are managed as separate power domains. Independent clock gating to the peripherals limits dynamic power by halting operation. Clock gating can be turned on and off quickly, although some leakage current occurs because the peripheral continues to receive power for biasing. Power gating tackles leakage by removing the biasing and can be applied on-chip or at the power supply. i.MX processors allow individual power gating to the Arm, PLL, and peripheral domains in standby mode.

In addition, i.MX processors use Dynamic Voltage and Frequency Scaling (DVFS), which reduces both frequency and voltage to complete required tasks with the lowest possible power consumption. The way the voltage and frequency are modified in response to changes of the load is determined in software. DVFS can be highly effective because power is reduced according to the square of the voltage. There is also Dynamic Process Temperature Compensation (DPTC), which adjusts the voltage in relation to die temperature to prevent power losses resulting from temperature increase.

Also, there is heterogeneous—or big.LITTLE—processing using a combination of Arm Cortex-A application processor cores and a Cortex-M microcontroller (MCU) core. The MCU core, running an RTOS, handles low-level and real-time tasks efficiently and allows the device to remain aware in a low-power state ready to wake the higher-performing Cortex-A cores when needed.

In addition, active well biasing allows CMOS transistors to be optimised for high performance in active modes while also minimising leakage in standby mode (he leakage can be reduced by up to 15 times).

Using system power modes to reduce power consumption

The various system power modes take advantage of the aforementioned features to slow down, halt, or turn off various parts of the device to save power while ensuring all required functions are performed properly. While in the Run mode, which is the normal operating mode, the core frequency and operating voltage can be dynamically changed within a range. In the Wait and Doze modes, certain clocks are gated, with operation resuming on receipt of an interrupt. In the State-Retention mode, the MCU and peripheral clocks are gated and the supply voltage is reduced to a minimum. There is also a Deep-Sleep mode in which clocks are gated, power to the Arm platform is turned off, and normal operation resumes on interrupt. In the Hibernate mode, on the other hand, all clocks and power domains are turned off and operation resumes in the same way as a cold boot.

Ultra-low-power devices can have even more system power modes to give extremely granular control: this is where the µPower subsystem of the i.MX 8ULP and i.MX 8ULP-CS families comes in, with a dedicated RISC-V core to manage the device’s 20 power modes.

This article has provided only an overview of the myriad mechanisms available to help manage the power consumption of applications running on i.MX 8 processors. Utilizing them to best effect demands extensive study that can still leave your application consuming more power than is ideal. At Anders, our embedded-systems engineers have extensive experience in minimising the power consumption of i.MX 8 processors and modules to achieve lower energy demands and longer battery life. Contact us today to find out how we can help your next design do more with less.