Interconnect technologies are the backbone of SoCs, including the emerging chiplet market.
The evolution from the early days of reusable semiconductor intellectual property (IP) blocks built by a couple of engineers in a garage to a $4.5-billion or so market segment has been a remarkable feat. While the growth, customer success, and economic impact of the processor IP market with companies like ARM, MIPS, and CEVA are well detailed, often overlooked is the contribution of interconnect IP and the network of connections that made it possible.
The IP business came about because of standardization, evolving from circa 2000 to 2010 when it became a business with third-party, pure-play IP companies. As soon as protocols were standardized, startups appeared offering PCI (and later PCI Express), USB, and memory controller IP blocks. Primarily EDA-only companies like Synopsys and Cadence realized that their customers would also outsource IP and look for dependable vendors to provide it. And so, they started acquiring IP startups and later extended their IP portfolios by internal development or more acquisitions. This is how the interconnect IP market came about.
Interconnect IP is today a healthy and growing market segment, a subset of the overall IP market, often referred to as the unsung hero because it doesn’t get as much attention as the processor/DSP IP market. Yet, IP interconnects are equally important components in the design of system-on-chip (SoC) devices and peripherals for interconnect. These interconnects integrate onto one SoC all the major functions that were traditionally separate, discrete chips on a computer or networking motherboard. Minimizing external components onto one SoC reduces size and cost and increases yield and efficiency.
A look back on IP interconnects reveals the evolution of standards such the Universal Serial Bus (USB), which was unveiled in 1996, PCIe, which was introduced in 2003, and Computer Express Link (CXL), which rolled out in 2019. Other protocols like Hyper Transport, RapidIO, Gen Z, CCIX, and OpenCAPI targeted specialized markets and applications. For example, RapidIO was successful in the wireless and industrial markets and later in high-reliability automotive and aerospace applications. Gen Z focused on optimized storage applications, while CCIX targeted accelerators. However, the lack of processor companies supporting these interconnects caused them to fade away, leaving PCI Express, USB, and others to dominate the market.
A view of the future reveals a growing demand for data-intensive artificial intelligence (AI) and high-performance computing (HPC) applications driving a need for high-bandwidth chip-to-chip interconnect technologies such as the Universal Chiplet Interconnect Express (UCIe), which was unwrapped in 2022.
The early days
Every chip design team had a small repository of designs and utilities shared and reused across multiple projects. Typically, these blocks of code were never fully documented, and support meant calling out across the cubicles to another engineer with knowledge about these legacy designs. Sharing IP and information across companies today is a well-accepted and proven methodology. Every semiconductor company has a centralized IP enablement team that maintains internal and external IP as well as providing support to various SoC design teams. Just like EDA procurement, IP acquisition has been centralized due to technical and economic factors.
In the late 1990s, typical systems were comprised of many different standard semiconductor chips like a CPU, a DSP, and memory interconnected on a PCB. Advancements in VLSI integration made it possible for more transistors on a single silicon die. This led to the integration of CPU and DSP Cores along with other higher-level functions and memories on silicon, which became SoCs. One of the earliest examples is the LSI Logic I/O processor chip developed for the Sony PlayStation-II design. As part of this, a set of tools and methodologies was developed for IP core-level integration and verification, which became the blueprint for similar complex SoC designs.
As an individual chip’s complexity increased, so too came an increasing need for data to be fed into it. Having different chips with different I/O protocols and electrical characteristics became untenable and led to interconnect standardization. The first generation of interconnects were slower and needed many pins. As complexity increased, the data bandwidth also needed to be increased while using fewer pins, leading to the development of high-speed serial interconnects in the early 2000s.
This form of IP interconnect became a foundational element for SoC success. The interconnection had to be sophisticated because the data was complex and needed error correction among other things.
Today, there are a variety of interconnect standards such as Ethernet, PCIe, and PCI Express. Over time, high-speed serial interconnects became popular for fewer pins and high-speed, high-bandwidth data transfers. From Generation 1 to Generation 6, speed and bandwidth multiplied. All these technologies and their five or six generations of standards found their niche in terms of where each can be applied.
Early on, USB was consumer-centric and became the consumer-friendly interconnect for PCs, laptops, and so on. USB was everywhere, even for storage with USB dongles, and it is available now for every kind of application. It’s also one of the easiest interconnects to use as plug-and-play (plug it in and it works). This is a great success showcasing companies coming together to create a standard and implementing their own version of this standard. PCIe was yet another IP standard that became popular in the compute, networking, and storage markets.
A new standard
While the aforementioned interconnects are outside the chip, there are also interconnects inside the chip, such as Arm’s AMBA, which includes the AXI and CHI protocols, for example. Inside the chip, there are many interconnected components connected through a standard fabric, which is referred to as the SoC fabric. The AMBA specifications are interconnects inside the chip. Outside the chip are the high-speed serial interconnects like PCIe, USB, and so on.
The new CXL standard extends PCIe connectivity and provides a pooling capability to share memory between chips. A data center architecture demands pooling or sharing of coherent memory between the CPU, GPU etc. so that every chip can read/write to the main memory coherently.
CXL enables a design to attach additional memory via PCIe. This is not as fast as the main DDR memory, but it’s available as an expanded memory through the CXL protocol.
The critical importance of standards
IP interconnect standards and their evolution are maintained and managed by industry standards consortiums comprised of big and small companies responsible for specifying open protocol specifications. Company representatives help set the standard and collaborate to ensure that standards are maintained, updated, and meet the needs of the industry.
Consortiums are structured in such a way that there are big companies who have the market need and muscle and budget to allocate additional resources to become the promoters. Big and small companies participate and contribute. Adopters use the technology without contributing. Students, consultants, and universities are another class of membership.
Many participating companies share their patents through the consortium to further a collective effort and level the playing field so all companies can make use of the standard without worrying about patent infringement. This is important because otherwise legal issues could ensue and slow adoption.
Apart from the specifications, these consortiums facilitate compliance and interoperability of standards interpreted by individual companies. They produce an interoperability requirement and certify it with their logos. Companies go to USB, PCIe, or Ethernet compliance labs to run tests that prove interoperability with the different chips resulting in a logo certification.
The industry consortium structure certainly helped move the market driven by needs, such as growth in internet, storage, data centers, and on-line shopping. Companies dropped their proprietary connectivity methodologies and adopted third-party, industry-wide standards.
Sure, the 600-pound gorillas of the market can still afford to have non-standard interconnects. Nonetheless, the industry needs standards consortiums because these collective efforts propel the market forward. The IP business itself is huge and its evolution is healthy and growing.
The emerging chiplet market
Standards consortiums create collaboration when the chip industry participates, and they will play a big role as SoCs evolve to chiplets and new interconnect standards emerge, such as UCIe.
Interconnect technologies are the backbone of SoC designs, including the emerging chiplet market. As monolithic chips become bigger and more complex, high yield becomes increasingly difficult. Building the whole chip becomes cumbersome and unwieldy, and few companies can afford it. The economics say to split the chip into blocks called chiplets, then stack them together into an application chip or 3D IC packaging.
Chiplets are a timely solution because of the slowing of Moore’s Law and increasing costs. That’s where the UCIe standard helps grow the ecosystem. Chiplets will require vendors to employ a standard interconnect that allows a chip design company to stitch them together. It is not easy to put multiple chiplets together in a 3D integrated chip. Skills are needed, and standards will help this industry move forward and build an independent standard chiplet market segment.
In theory, it’s great to have standards-based chiplets. In practice, it is not that straightforward. A chiplet strategy depends on another company’s chiplet that needs to be integrated and verified. Unlike SoC designs, verifying 3D ICS are much more complex and this issue needs to be resolved fairly quickly for the market to flourish.
Certainly, this industry must progress further before using third-party chiplet IP becomes a standard practice. The future of large semiconductor development is based on 3D ICs with many chiplets from internal and external sources. That is the next step. The industry is not there yet. UCIe is a step forward.
Conclusion
Interconnect standards and IP played a critical role in the adoption of SoC design methodologies enabling the acceleration of the development of electronic products. Industry consortiums led the way.