A novel PHY may be the answer to the packaging question
Early adopters in the chiplet arena face a dilemma. In pursuit of the highest possible performance and density, the most widely discussed chiplet designs depend upon silicon interposers (or their close relatives, embedded silicon bridges) as a substrate for mounting and interconnecting the multiple dice.
Fabricating the inter-die connections on a silicon substrate allows much tighter bump spacing and line spacing, meaning more possible connections per millimeter of die edge, and hence greater inter-die bandwidth per millimeter of die edge. Also, for a given interconnect electronics, silicon offers a higher data rate than conventional organic substrates. For datacenter CPUs and GPUs, where density and performance are non-negotiable and price is secondary, the common belief has been, as one vendor recently said, “without interposers there can be no chiplets.”
Not the only way
But silicon interposers have some concerning characteristics, particularly for product roadmaps that need to grow beyond high-end, price-insensitive niches. Interposers are expensive relative to conventional packaging: the largest cost upwards of $1,000 in volume. This limits interposer technology to applications that can absorb that kind of cost.
Further, there is a strict limit on the maximum size of the interposer—today, about 2,500mm2 in production, with plans to reach 3,300mm2. But 2,500mm2 is only about a quarter the area of standard organic- substrate packages that are manufacturable in volume today. So, ironically, use of the silicon interposer actually limits the number of chiplets that can be placed on one substrate, and thus limits parallelism.
Another issue limits the applications in which interposers can be used. Those tightly spaced microbumps have a downside: they are fragile. Today, microbump assemblies cannot meet the shock and vibration requirements of some key market segments, such as aerospace and automotive.
And, from a business point of view, silicon interposer technology is proprietary—usually bundled with die fabrication and assembly at a single vendor. In today’s global trade environment, no one needs an explanation of the impact of a single-source assembly on continuity of supply.
Does a system designer have to accept these risks? In some cases, yes. But there are alternatives. Many widely used CPUs today are in fact multi-die assemblies built on standard organic substrates. And the two most prominent emerging standards for chiplet interconnect—UCIe and the Open Compute Project’s (OCP’s) Bunch of Wires (BoW) both define lower- speed implementations using organic substrates. This raises an obvious question: is there a design solution that offers the performance advantages of silicon interposers without their drawbacks, risks, and limitations?
The PHY is the key
To find out, we must look at the dice themselves; specifically, at the tiny electronic circuits that drive the interconnect lines.
Where large amounts of data must move quickly— between a CPU and a GPU, for instance, or between a processor and a cluster of memory dice—designers use high-speed serial I/O schemes. This is the way computers move data between chips on a circuit board using the PCIe standard.
In fact, most of today’s proposed chiplet interconnect standards use a physical-layer (PHY) IP block derived, in one way or another, from the original PCIe PHY developed for backplane use. These new designs omit functions that are not necessary in the extremely restricted and carefully controlled world of signals between nearly touching dice on an interposer. So, they are smaller and consume less power than the PCIe PHY but can move streams of data at very high speeds across a few millimeters of silicon interposer.
There is another PHY technology, however. Coming out of the same development team that produced the PHY adopted for the BoW standard, the NuLink PHY from Eliyan goes beyond its predecessors in optimizing high-speed serial transmission for chiplet use.
As a more advanced design, it exceeds the performance of today’s UCIe and BoW PHYs and—critically—it reaches performance levels on organic substrates that alternative PHYs achieve on silicon interposers.
This opens up the roadmap for chiplet-based multi-die designs. Using the NuLink PHY, designers can get
high performance on silicon interposers and on organic substrates, thereby providing their product lines with access to today’s most demanding applications and to more cost- sensitive market segments and to segments with rigid mechanical or thermal requirements. Further, organic substrates give the roadmap far greater supply-chain diversity.
The NuLink PHY
Eliyan has incorporated into the NuLink PHY some specific characteristics to make these benefits possible. First, on silicon interposers or bridges, the NuLink PHY can deliver twice the bitrate at lower power consumption, in a given technology, compared to alternative PHYs. This means more absolute bandwidth between dice, more bandwidth per millimeter of die edge on a chiplet, and less of the system power budget going to interconnect.
Additionally, the NuLink PHY is inherently bidirectional. It can be used in a unidirectional mode to support UCIe- or BoW- compliant interfaces. It can also be used in a dynamically switchable bidirectional mode to directly support the switched bidirectional datapaths of most DRAMs or the UMI (Universal Memory Interface) interface presented at the OCP Summit by Eliyan. This capability can eliminate half of the lanes necessary to implement a processor-to- memory connection, creating huge savings in die-edge area and power. In applications using proprietary interconnect architectures, the NuLink PHY can also operate in a fully bidirectional mode when provided with some additional circuitry for functions such as echo cancellation.
Together, these features offer designers the highest achievable performance on silicon substrates, whether using interposer, embedded bridge, or some emerging technology. They also offer power savings, reductions in critical die-edge area, and placement flexibility. And, as a building block, the NuLink PHY can be used to implement either UCIe-compliant, BoW- compliant, UMI-compliant, or custom connections.
The organic alternative
The advantages presented above would be more than sufficient to consider the NuLink PHY IP for high- end designs using silicon substrates. But one more feature of the NuLink PHY expands the scope of this discussion greatly. That is the PHY’s ability to deliver the same performance over ordinary organic laminate substrates that alternative PHYs deliver only on silicon substrates. That is, up to 4.5Tbits/s per millimeter of die edge in bandwidth, and no more than 0.5pJ/ bit energy consumption during transfers. Further, on organic substrates, the NuLink PHY expands its reach to 20mm, thereby enabling other benefits.
This fact opens many important possibilities to the system designer. For one, it means that on high-end designs, designers can use an organic substrate instead of a silicon substrate and have four times the substrate area. That of course means more dice on the substrate, with resulting increases in board- level component density as well as reductions in power, increased system performance, and increased security from moving more board-level interconnect into the packages. The move to organic substrates will also free the design from the inherent risks of single-source advanced packaging and test.
Second, the NuLink PHY can deliver this performance across a range of 20mm on organic substrates, while advanced packaging requires dies to be virtually abutting—with only 0.1mm separation—in order to reach full speed. This means far more flexibility in placement and routing on the substrate. It also means it is possible to place hot ASIC dice further away from temperature-sensitive high bandwidth memory (HBM) stacks, thereby allowing for increased thermal isolation. This is critical because an advanced ASIC running at full speed can easily radiate enough heat to overheat HBM dice mounted right next to it. This can force physical separation that will limit memory bandwidth and waste interposer area.
Perhaps even more significantly, the ability to use organic substrates opens new markets for the product roadmap.
Such substrates can be qualified for aerospace, automotive, and demanding industrial markets.
The developer can plan for a wide range of branches in the product roadmap. These could include higher- density offerings exploiting the larger organic substrate for greater parallelism and performance. There could be branches into new market segments not willing to accept silicon substrates. Or there could be extensions into highly cost-sensitive or very high- volume consumer markets that would struggle with limited silicon interposer supply. And use of organic substrates can allow the multi-die assembly to be built and tested by any of a wide variety of outsource vendors, assuring supply-chain continuity during unanticipated disruptions and giving flexibility to meet local- content requirements.
Thus, the NuLink PHY is not just a higher- performance alternative for supporting existing inter-die standards on existing silicon substrates. By opening the alternative of organic substrates, it is also the key that unlocks new markets, new line extensions, and freedom from a range of worries about continuity of supply. That is quite a bit of leverage for a small piece of silicon IP.